Interconnection technology is constantly challenged to satisfy the ever increasing requirements for high density and performance associated with ultra large scale integration semiconductor devices. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the R×C product, the more limiting the circuit speed. As integrated circuits become complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes, e.g., less than about 0.12 micron. The rejection rate due to integrated circuits speed delays in sub-micron regimes has become a limiting factor in fabrication.
The dielectric constant (k) of materials currently employed in the manufacture of semiconductor devices for an interlayer dielectric (ILD) ranges from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of the dielectric constant (k) expressed herein is based upon a value of one (1) for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permitivity have been employed. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9, e.g., less than 3.5. Porous low-k dielectric materials, e.g., dielectric materials having a porosity of 1% to 70%, offer promise, such as porous SiLK™ available from Dow Chemical, located in Midland, Mich., and JSR5108 or JSR5109 available from JSR, located in Japan. In attempting to employ such porous low-k dielectric materials in interconnect technology, as for a dielectric layer in damascene techniques, various issues arise. For example, upon forming an opening in such a porous dielectric material, the sidewalls defining the opening have exposed pores. As a result, it is extremely difficult to deposit a continuous barrier metal layer lining the sidewalls without discontinuities stemming from the presence of such exposed pores.
Adverting to FIGS. 1A–1C, reference character 10 generally denotes a substrate which may include various devices formed in a semiconductor substrate as well as overlying layers. Reference character 12 denotes a porous dielectric layer, such as porous SiLK™, formed on an etch-stop layer 11, such as silicon nitride. A capping layer 13, such as silicon nitride, is formed over porous dielectric layer 12, and a photoresist mask 14 is formed thereon. An opening 100 is etched, using the photoresist mask 14, which opening 100 is defined by sidewalls in porous dielectric layer 12 and sidewalls in capping layer 13 and etch-stop layer 11, as shown in FIG. 1B. Since dielectric layer 12 is a porous dielectric material, various pores 15 are exposed on the sidewalls upon forming opening 100.
As microminiaturization proceeds apace, it is extremely difficult to deposit a continuous barrier metal layer, such as tantalum or tantalum nitride, lining an opening. This problem is exacerbated when the sidewalls of the opening contain exposed pores 15. Upon depositing barrier metal layer 16, various discontinuities occur, particularly in regions having exposed pores 15, as schematically illustrated in FIG. 1C.
Accordingly, a need exists for methodology enabling the fabrication of semiconductor devices having reliable interconnects with uniformly deposited barrier metal layers without discontinuities. A particular need exists for methodology enabling the fabrication of such semiconductor devices having copper (Cu) or Cu alloy interconnects using low-k porous dielectric materials.